Designing a digital ASIC involves many different tasks, some carried out by the ASIC designers, while others are taken care of by the ASIC vendor. BitSim has the knowledge and experience in many of these areas, from Hardware System Design to Manufacturing Test Methodologies. Since a digital ASIC cannot be changed once it is manufactured, verification of its functions is crucial before the masks for production are made. Therefore, there is a large effort needed to simulate the design at different levels to verify that no bugs exist. Within BitSim, many engineers have significiant experience of methods and tools for ASIC verification. The ASIC design is described using a Hardware Description Language, HDL. There are a number of languages available such as Verilog, VHDL, System C or System Verilog. The language can describe the hardware at different levels of detail. The most common level used today is called Register Transfer Level, RTL. This level describes the functions of the ASIC with logic relations between memory elements (registers).
The programmed functions are simulatable to verify their correctness, but they also need to be translated into hardware i.e. logic gates. This is called synthesis and is done using software tools. The result of the synthesis must be verified, both from a functional and a timing perspective. The function can be verified by gate level simulations or by comparing the logic produced by synthesis to the programmed functions in the HDL. The latter is called formal verification or equivalence check. A floorplan/layout tool places the logic gates generated during synthesis on a model of the physical ASIC. This enables the calculation of signal delays between all logic elements.
Static Timing Analysis (STA) is used to constrain the layout tools and to verify that the design will work at the specified frequency. When the ASICs are manufactured, each chip needs to be tested in order to secure that all delivered devices work properly. The ASICs are tested using test vectors, which can be either functional vectors or automatically generated vectors, or both. Functional vectors applies signals to the ASIC similar to signals the ASIC would receive in a real environment. Automatically generated vectors on the other hand is only applying signals to verify that no defects exist within the ASIC, with no relation to how the ASIC will be used in its target environment. To be able to implement ATPG (Automatic Test Pattern Generation), special test logic needs to be designed in. This area of work is called Design For Test (DFT). BitSim has experience from numerous ASIC projects, having done synthesis, gate level simulation, formal verification/equivalence check, static timing analysis, design for test and automatic test pattern generation.
