ASIC DFT Design & Implementation
This device is a complex SoC (System On Chip) 0.12 u ASIC with multiple CPUs, SRAM, Bluetooth, IrDA, DMA, Flash, UART, interrupt ctrl, I2C, GPIO and a LCD Controller.
BitSim's responsibilities included the design of DFT, BIST, Scan chains, Boundary Scan, ATPG (Automatic Test Pattern Generation) in the role of DFT design engineering and project lead. BitSim was also responsible for the top level design data base, functional verification using Cadence Specman and the gate level verification.
