BADGE Features

BADGE is a modular design which in turn makes it very flexible. The block architecture of BADGE is depicted in the figure below, which shows the basis of the modularity.

BADGE has numerous features, from flexibility and scalability to hardware acceleration and application development utilities. We start from the HW perspective with BADGE's block architecture and pair each block with the relevant functions they offer. This way, it is easy to see how BADGE meets your requirements, and learn about the different available blocks in BADGE. And if there is something you would like to have adapted or added.

Since BADGE is an IP core, there are features that are not included in the block architecture description below as this is a pure hardware-oriented view. Software utilities exist to convert usual formats of pictures, fonts and data to fit your specific BADGE configuration. Of course, the BADGE IP also includes all necessary documentation.

 

 

Display controller

This block is responsible for reading from the graphics memory and transmitting the data as an image to the display. It includes a number of settings to accommodate different kinds of display types and parameters. The display controller also controls the overlay between video and graphics data, when video is enabled. If several displays with different display data are required, more than one instance of the display controller can be used (one for each display).

• Up to 4096x4096 pixels resolution.
• Graphics and video overlay, using a video key color (allowing arbitrary shapes for the video area).
• Flicker free. Single, double or multi buffering.
• Alpha blending.
• LVTTL and/or LVDS output (can be used for DVI output).
• Hardware cursor (sprite).
• Color-Look-Up-Table (CLUT).

 

Host interfaces

The host interface block is the contact between BADGE and the CPU. The data bus width varies between 8, 16 and 32 bits for different processors (but could easily be made serial) and the address bus width is fully scaleable between 0 and upwards. The interface is easy to adapt to any host processor, and scale to meet the requirements for the target application.

• Currently available host interfaces: ARM 920T, Microblaze/OPB, Microblaze/FSL, Avalon/Nios/Nios-II, i386EX, VLIO/XScale, Renesas M32c, NEC V850, Samsung 2440 ARM.
• Easily adapted to any host processor.
• Serial or parallel data transfer.

 

Memory interfaces

The memory interfaces translate between the internal BADGE memory accesses, to accesses fit for the specific type of memory connected to BADGE. The width and depth of the connected memories can be easily scaled up or down depending on the current BADGE implementation and application needs. Currently available memory interfaces:

• SRAM
• ZBT SRAM
• SDRAM
• DDR SDRAM

 

GPUs - Graphics Processing Units

The GPUs are the basis of all acceleration in BADGE. Each GPU is specialized in doing certain types of operations very fast. Since the GPUs are separate modules, each can be included/discluded independently of each other. However, some functionality in the GPUs depends on an operation in another GPU for the entire graphics operation to be complete.

 

CHRGPU - CHaRacter GPU

The CHRGPU interprets a font table stored in the graphics memory and use this to print characters as they are received from the CPU. A software conversion utility is available which convert from every font format supported by the FreeType (www.freetype.org) library (such as TrueType, Type 1, X11 PCF etc.)  to BADGE's font format.

• Background and foreground color can be set for each character.
• Can use compression for sparsely populated fonts.
• Up to 23 bits wide character codes.
• Support Unicode-16 in Basic Multilingual Plane.
• Transparent printing available (no background color used).
• Anti-aliased text using alpha values.
• Printing in four different rotations: 0, 90, 180 and 270 degrees.
• Automatic increment of print position for each character written.
• Clipping box functionality - text written outside the clipping box is not visible.

 

VPU - Video Processing Unit

The VPU enables streaming video in sync with the graphics in BADGE. Overlay of video and graphics is supported using a video key color which makes it possible to have the video area be any arbitrary shape (like a circle). The overlay functionality is handled in the display controller.

• 8/16-bit Digital RGB input according to ITU-R BT.656.
• Analog video sources is possible with an analog video decoder.
• Both 50 and 60 Hz video refresh rate.
• Automatic detection of video refresh rate.
• Support deinterlace.
• The video can be scaled with a factor between 0.5 and 2.0 to make it fit full screen on most screen sizes.
• The video can be rotated in four directions: 0, 90, 180 and 270 degrees.

 

RCCGPU - ReCtangle Copy GPU

The RCCGPU operates on rectangles, manipulating the data according to the requested operation.

• Draws filled rectangles in sizes from 1x1 to 4095x4095 pixels.
• Draws horizontal and vertical lines.
• Copies rectangles with any general data (BitBLT - Bit BLock Transfers).
• Copies rectangles with Raster OPerations - ROP.
• Transparent copying (using a specific transparency color).
• Alpha blending copying.
• Can copy data between continuous and discontinuous data areas.

 

SPDGPU - Simple Pixel Drawing GPU

The SPDGPU's main feature is drawing lines of arbitrary length and direction, but also comes in handy for other graphics operations, as drawing polygons.

• Draw points, lines, unfilled polygons and filled rectangles.
• Draws lines using an implementation of the DDA line algorithm between any two coordinates.

 

MDAGPU - Memory Direct Access GPU

The MDAGPU operates directly on separate pixels and does as such not provide any distinct acceleration. Reading and writing directly to the graphics memory from the CPU is translated into MDAGPU commands by the host controller.

• Direct-mapped memory accesses.
• Automatic incrementing of internal address pointer for DMA-like reads or writes.

 

SIGPU - Serial Inflate GPU

The SIGPU supports decompression of compressed data. Compression of data saves memory space and decreases start-up time. For the SIGPU the data is loaded serially into the Inflate Unit. Any data can be compressed: pictures, bitmaps, fonts or arbitrary data.  A software conversion utility is available for compressing data to a format readable by the SIGPU.

The compression is based on the Deflate algorithm that combines high reliability with good compression, good encoding speed with excellent decoding speed.

The SIGPU is master on an external SPI bus for accessing several different types of SPI flash memories. The flash memory can be used for storing font, bitmap and arbitrary data.

• Decompress compressed data stored in an SPI flash to the graphics memory.
• Support DEFLATE IETF RFC 1951 compression with fixed Huffman codes.
• Copies uncompressed data stored in an SPI flash to the graphics memory.
• The Inflate Unit can be adapted to other memory interfaces.