To design an FPGA, several steps are needed, using specific CAE tools. Some general tools support more that one FPGA vendor, while FPGA vendors themselves supply special tools. The FPGA is described using a Hardware Description Language, HDL. There are a number of languages available such as Verilog, VHDL, System C or System Verilog. The language can describe the hardware at different levels of detail. The most common level used today is called Register Transfer Level (RTL). This level describes the functions of the FPGA with logic relations between memory elements (registers).
Simulation is an important step. This is to verify that the function is operating as intended. Since it is no problem to program the FPGA and test it on board level, heavy simulations that might take days can instead be verified in real time on the board in a matter of hours. However, when doing the detailed simulation it is important to have control of the verification process.
When the design looks correct in simulation it is time to start the synthesis. The HDL language is translated to FPGA specific building blocks. Major FPGA vendors have their own synthesis tools, but there are also several tools that can handle more than one FPGA vendor. From the synthesis it is possible to generate a netlist and a timing file, to perform a timing simulation using the same simulator as before.
When Synthesis is done it is time for place and route. It is always a vendor specific tool that does a placement of the building blocks created by the synthesis tool. The place and route tool generates a netlist and a timing file. With the timing file it is possible to perform a timing simulation again, in the same simulation environment as before. This timing simulation will be more accurate than the one from synthesis, since it involves timing for routing as well. BitSim has experience from numerous FPGA projects, with several different vendors such as Altera and Xilinx, (see partner programs link).
