High-Speed Serial Protocols

The technology for how to transmit data serially with high speed has been known for a long time thanks to developments within the telecom industry, with some well known standards (for example Gigabit Ethernet). New protocols have been added especially intended for communication between components on a circuit board. Roughly speaking it is possible to divide the different standards in the ones intended for short-haul communication. The applications areas for these are overlapping, and the actual limitation for distance is more dependent on the media used (such as copper on FR-4, fiber, coax, twisted pair). From a technical view it is possible to run Serial RapidIO over STP/UTP cable, or to use Gigabit Ethernet in between boards in a subrack.

Standards for transmission over short-haul (on or between circuit boards)

The communication is made over an ordinary FR-4 laminate, and the maximum performance is mostly limited to some features of the laminate, such as frequency dependent losses. Among these there are three competing "address based" standards: - PCI Express - Serial RapidIO and- HyperTransport. If you like, they can be seen as serial replacements of good old buses such as VME or PCI (thus the term "address based"). As an example, PCI Express is seen as a direct replacement for PCI, and the standard is developed in such as a way that it is simple to migrate from PCI to PCI Express. If you prefer to see PCI Express primarily as a an alternative to communicate between boards in a subrack, then Serial RapidIO can be seen as a powerful way to connect things such as clusters of DSP processors (Texas Instruments, Freescale) or between communication processors (e.g. Freescale PowerQuicc). HyperTransport is almost synonymous with AMD (used as the local bus in their chip sets for PC), but it is an open standard with similar capacity to RapidIO. HyperTransport products are more geared towards implementations around AMDs/MIPS, the more powerful processors and chip sets. Therefore it appears that RapidIO and PCI Express are more likely to dominate in a more general embedded environment. Other standards for short-haul have been developed for specific PHY-components, for example XAUI to 10 Gigabit Ethernet and the more general SPI-4.2 protocol common within ATM and "packets over SONET/SDH" (POS-PHY level 4). In its basic principle all the above standards use the same basic technology, whether the main ingredients are called SERDES or CDR. SERDES stands for "serializer de-serializer" and it is basically an ordinary parallel-to-serial , serial-till-parallel conversion. The interesting thing is CDR, (Clock Data Recovery), which means that the clock is recovered from the data stream on the receiver side. This is achieved by never letting the data stream be static for any longer period. It must toggle a minimum number of time during a given period of time. This is guaranteed by using a coding technique called "8b/10b" coding which is put above the data stream to be transmitted. 8 bits are coded into 10 bits before they are sent, which means that you loose 20 percent transmission capacity.

Standards for transmission in mid-range distance

The protocols here are well known: Gigabit Ethernet, Fibre Channel etc. Again, technically there is no problem to use these on short-haul communication. And for the telecom board and packaging standard ATCA (PICMG 3.X) it is actually defined as alternatives for inter board communication.

FPGA

The major suppliers of FPGAs have realized that FPGAs will be a key component for the future development of high-speed solutions. They have therefore been early in offering high-speed interfaces with hard macro I/O supporting SERDES. Hence they can offer support for all the above standards. The key functions offered are SERDES, CDR, 8b/10b coders and decoders. In addition to this specific protocol, IP blocks are available. Most IP has a purchase fee, but there is also free IP supplied by the vendors for quick and simple communication solutions between two FPGA:s.

Problems

To successfully compete with the SERDES implementations, the design engineer needs a solid knowledge in signal integrity (SI) and knowledge of when to use these in practical design, such as in CAD constraints. It is crucial that rules are followed for shaping the power/ground plane, and that filters and decoupling is done in a proper way. Potential cross-talk between wires must be controlled via design rules and the utilization of the different board layers. Furthermore, wires must be drawn without sharp corners and preferably without changing layer. Impedance matching is an important factor. BitSim with its high-speed specialists can support you to succeed in your design in the shortest time at a low risk. We help our customers with optimal solutions whether it is in protocol knowledge, component selection, board stackup, layout expertise, or simulation solutions. BitSim has, after a qualification process, been approved by the leading FPGA supplier Altera as a ACAP (Altera Certified High-Speed I/O Design Partners)