Overview
NIOS® II, from Altera Inc., is a configurable 32-bits soft processor which 2004 replaced the old NIOS. The major difference compared to MicroBlaze is that the processor is scalable in three different versions: Economy, Standard and Fast. To give a picture of the NIOS II/f (fast) core its area is approximately 35 percent bigger than the Standard core, but in return the Dhrystone result is increased by 50 percent. The latest software for Nios II Embedded Design Suite is version 6.0. The processor kernel can be implemented in Altera's FPGA architectures: Cyclone II, Stratix and StratixII. The processor can be used in Cyclone (not a common choice for new projects) but with decreased performance because lack of multipliers in the hardware architecture.
Architecture
NIOS II uses "Little-Endian" format (Bit 31 is most significant) for address and data. The standard configuration includes: 5-step pipeline (6-step for fast core), instructions cache, hardware multiplier, division and shift, 32 external interrupt handlers priority is made in software, simple floating point instructions, locally memory interface, hardware accelerator interface, debug-logic etc.
Development Tools and Operating Systems
The NIOS II core is licensed as a part of EDS, Embedded Design Suite. SOPC Builder is the tool used to configure IP cores for different peripherals and assemble your embedded system for Altera FPGA:s. In the Eclipse-based Integrated Development Environment (IDE) you find: software-templates, compiler (GNU), debugger, and the new C-to-Hardware Acceleration (C2H) Compiler (separate license). The current version of NIOS II does not implement a virtual memory management unit (MMU). This limits the selection of real-time operating systems (RTOS) available for the processor. One commercial RTOS that supports Nios II is Nucleus. eCos and uCLinux are also interesting alternatives since they are royalty-free for new products and are open-source. More information on the NIOS II ports of these RTOS:s can be found on Nios Forum.
Design Tips
The many ways of configuring NIOS II gives freedom under responsibility. It is important to understand the system effects caused by configuration choices. In the subsequent sections we want to give you some general tips to help you get the most of your NIOS II design. It's always good to try out different configurations of the processor core before choosing one for a new project.
Processor Interfaces
NIOS II communicates through the Avalon bus. The bus uses slave-arbitration, which means that different masters can use different slaves at the same time. The Avalon structures offers separate dedicated data and address paths per master, and uses arbitration only when accessed by more than one master at the same time e.g. when two masters wants to use the same memory. SOPC builder is easy to use when building an embedded system with NIOS II (master). The Avalon bus (switch fabric) is used to connect peripherals as: GPIO, SPI, UART, Ethernet and external memory controllers. This bus is also used to connect custom IP blocks e.g. hardware accelerators like the Bitsim Accelerated Display Graphics Engine (BADGE).
Performance
A NIOS II system can implement data- and instructions-cache. To get the best performance use tightly coupled memories, which are fast-access, on chip memories. The list below contains options to add for higher performance:
- Add instruction cache (if your application execute from external memory)
- Add data caches (if your application accesses external memory)
- Add barrel shifter
- Add multiplier
- Add integer divider
Instruction caches are normally more important than data caches even if they are small. Note that small data caches can have worse performance than no data cache at all (due to thrashing and cache-line fetching).
NIOS II Multi Processor System
Use of multiple processor system can increase performance of the system but it also makes it more complex. Normally the Avalon bus and peripherals are separated but with the Mutex kernel (IP block) it is easy to coordinate shared resources. SOPC builder configures the processor system hardware and with IDE software (Eclipse) and debugging takes place. An extra help is Signal-TAP (Altera's own logic analyzer) for debug of data and address bus.
