The verification of a complex digital systems takes more and more time in a development project. The costs for hidden errors have dramatically increased during the last years, especially considering the short market windows for products of today. To find a critical error late in the product cycle is costly. Therefore, the way your system is verified is critical. How can the verification work be performed in an effective way? How can the time and resources be minimized? It is extremely important to select a working verification methodology. Some things to consider are:
Planning
- Strategy
- Bottom-up or top-down, simple functional or higher level models
- Develop or purchase
- Regression tests
- Document Requirements
- Quality, decisions points (when is verification completed?)
- Verification plan
- Personnel
- Tools
- Time Schedule
- Version control
- Bug Report Handling
Specification
- Functional specifications (all functions must be possible to verify)
- Verification specification (test cases, coverage requirements)
- Test environment
Implementation
- Test benches
- Design and/or configuration
- Verification of the test environment
- Simulation models (internally developed or externally sourced)
- Tools (VHDL/Verilog)
Execution
- Simulation
- Static Timing Analysis
- Verification reports
- Reviews
