Verilog

Verilog is a hardware description language. Another well established language is VHDL. With Verilog and VHDL, hardware can be expressed in a syntax just as in a software language, but with one big difference - the code is normally describing a behaviour that is parallel, not serial.

Verilog can express functionality without any clock, Behavioural Verilog, also known as Transaction Level Modeling, or functionality with a common synchronous clock, Register Transfer Level, or as a netlist called structured Verilog. In the beginning the intent was to use behavioural code to model everything. But it proved to be too difficult to create the tools and methodologies that were needed. Today, normally RTL-level code is used, where a common synchronous clock is the base, with boolean expressions describing the input to the flip-flops. All events occur on the rising edge of the clock.

With Verilog, digital systems (gates and flip-flops) can be described in a textual form, independent of the target device itself. The Verilog code can then be automatically converted and optimized, and mapped to a specific hardware using the synthesis- and place and route-tools. The end device is normally a user defined hardware such as a PLD (Programmable Logic Device), an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). For example, in an ASIC design, Verilog code is written, and during synthesis the RTL code is transformed into a netlist format which gives the exact net of the ASIC gates and flip-flops to be used in the final implementation. All signal paths are routed so that all timing constraints are fulfilled. The Place and route tool maps the netlist into physical design.

The Verilog language allows descriptions of both sequential and parallel digital data flows. All Verilog can be simulated and all signals in the design can be traced in a waveform window. The Incisive tool from Cadence (TM) is an example of a simulation tool used for this. The advantage in using Verilog for hardware design is that it is easy to describe the functionality of the design and to simulate. In addition it is a vendor independent standard with many different third party tools available. Finally, it is independent of the hardware that is to be used.

The Verilog language is similar in syntax to ordinary C. Verilog is a public domain language and is presently dominant in the US and Japan, while VHDL dominates in Europe. BitSim offers module-based proprietary ready-to-use blocks often called IP, Intellectual Property. These IPs are packetized digital systems with various functions. This allows BitSim's IPs to be incorporated into other digital system in a straightforward way.