VHDL is a hardware description language. Another well established language is Verilog. With VHDL and Verilog, hardware can be expressed in a syntax just like a software language, but with one big difference: The code can be executed in parallel, (all concurrent statements in the design is executed in parallel) as opposed to software language which is executed strictly linear.
VHDL can model the functionality without any clock, Behavioural VHDL, also known as Transaction Level Modeling, or the functionality with a common synchronous clock, Register Transfer Level, or as a netlist "netlist VHDL". In the past, methodologies and tools were developed to enable the usage of behavioural VHDL, but these did not prove to be effective enough. Today, normally RTL-level code is used, where a common synchronous clock is the base, with boolean expressions describing the input to the flip-flops. All events occur on the rising or the falling edge of the clock.
With VHDL digital systems (gates and flip-flops) can be described in a textual form, independent of the target device itself. The VHDL code can then be automatically converted and optimized, and mapped to a specific hardware using the synthesis- and place and route-tools. The end device is normally a user defined hardware such as a PLD (Programmable Logic Device), an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). When a digital system is considered as debugged and finished a target device is selected and the VHDL-files are transformed into a netlist (through a process called synthesis). The final configuration is called Place & Route, and involves placing of the gates and the flip-flops onto the specified target architecture. All signal paths are routed so that all timing constraints are fulfilled. Major parts of these processes are automated. However, each step can be manipulated if the designer chooses to change a specific parameter.
The VHDL language allows descriptions of both sequential and parallel digital data flows. All VHDL can be simulated and all signals in the design can be traced in a waveform window. An example of a simulation tool for such kind of analysis is e.g. Modelsim from Mentor Graphics. The advantage in using VHDL for hardware design is that it is easy to describe the functionality of the design and to simulate. In addition, it is a vendor independent standard with many different third party tools available. Finally, it is independent of what hardware to be used.
The VHDL language syntax is based on the software langauge ADA. The power in using VHDL and FPGAs is that the development time can be kept short at the same time as future compatibility is ensured. There is no risk of an FPGA reaching an End-of-Life (taken out of production) since VHDL is standardised so that future FPGAs can be configured with any VHDL code. BitSim offers module based proprietary ready-to-use blocks often called IP (Intellectual Property). These IPs are packetized digital systems with various functions. This allows BitSims IPs to be incorporated into other digital system in a straightforward way. *VHDL = VHSIC Hardware Description Language, VHSIC = Very High Speed Integrated Circuits, both VHDL and VHSIC were US Department of Defence funded research Projects.
begin-- Divide clock by four
process(clk, reset_n)
begin
if (reset_n = '0') then
clk_cnt <= (oth => '0');
clk_div <= '0';
elsif clk'event and (clk = '1') then
clk_cnt <= clk_cnt + 1;
if clk_cnt = 0 then
clk_div <= '1';
else
clk_div <= '0';
end if;
end if;
end process;
